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8734b?seepr?9/2012 features ? low-voltage and standard-voltage operation ? v cc = 1.7v to 5.5v ? internally organized as 16,384 x 8 ? 2-wire serial interface ? schmitt trigger, filtered inputs for noise suppression ? bidirectional data transfer protocol ? 400khz (1.7v) and 1mhz (2.5v, 2.7v, 5.0v) compatibility ? write protect pin for hardware protection ? 64-byte page write mode ? partial page writes allowed ? self-timed write cycle (5ms max) ? high reliability ? endurance: 1,000,000 write cycles ? data retention: 40 years ? lead-free/halogen-free devices available ? green package options (pb/halide-free/rohs compliant) ? 8-lead jedec soic, 8-lead tssop, 8-pad udfn, 8-pad xdfn, and 8-ball vfbga packages ? die sale options: wafer form, waffle pack, and bumped wafers description the atmel ? at24c128c provides 131,072-bits of serial electrically erasable and programmable read-only memory (eeprom) organized as 16,384 words of eight bits each. the device?s cascading feature allows up to eight devices to share a common 2-wire bus. the device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential. the devices are available in space-saving 8-lead jedec soic, 8-lead tssop, 8-pad udfn, 8-pad xdfn, and 8-ball vfbga packages. in addition, this device operates from 1.7v to 5.5v. atmel at24c128c i 2 c-compatible (2-wire) serial eeprom 128-kbit (16,384 x 8) datasheet
2 atmel at24c128c [datasheet] 8734b?seepr?9/2012 1. pin configurations and pinouts table 1-1. pin configuration 2. absolute maximum ratings* pin function a 0 address input a 1 address input a 2 address input gnd ground sda serial data scl serial clock input wp write protect v cc device power supply 8-pad udfn/xdfn v cc wp scl sda a 0 a 1 a 2 gnd 1 2 3 4 8 7 6 5 8-ball vfbga bottom view a 0 a 1 a 2 gnd 1 2 3 4 8 7 6 5 8-lead soic v cc wp scl sda 8-lead tssop top view top view 1 2 3 4 8 7 6 5 a 0 a 1 a 2 gnd v cc wp scl sda top view a 0 a 1 a 2 gnd v cc wp scl sda 8 7 6 5 1 2 3 4 operating temperature . . . . . . . . . . . ? 55c to +125c storage temperature . . . . . . . . . . . ? 65c to + 150c voltage on any pin with respect to ground . . . . . . . . . . . . . . ? 1.0 v +7.0v maximum operating voltage . . . . . . . . . . . . . . . 6.25v dc output current. . . . . . . . . . . . . . . . . . . . . . . 5.0ma *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification are not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability.
3 atmel at24c128c [datasheet] 8734b?seepr?9/2012 3. block diagram 4. pin descriptions serial clock (scl): the scl input is used to positive-edge clock data into each eeprom device and negative-edge clock data out of each device. serial data (sda): the sda pin is bidirectional for serial data transfer. this pin is open drain driven and may be wire-ored with any number of other open-drain or open-collector devices. device addresses (a 2 , a 1 , a 0 ): the a 2 , a 1 , and a 0 pins are device address inputs that are hard wired (directly to gnd or to v cc ) for compatibility with other atmel at24c devices. when the pins are hard wired, as many as eight 128k devices may be addressed on a single bus system. (device addressing is discussed in detail in section 7. ?device addressing? on page 9 ). a device is selected when a corresponding hardware and software match is true. if these pins are left floating, the a 2 , a 1 , and a 0 pins will be internally pulled down to gnd. however, due to capacitive coupling that may appear during customer applications, atmel recommends always connecting the address pins to a known state. when using a pull-up resistor, atmel recommends using 10k ? or less. write protect (wp): the write protect input, when connected to gnd, allows normal write operations. when wp is connected directly to v cc , all write operations to the memory are inhibited. if the pin is left floating, the wp pin will be internally pulled down to gnd. however, due to capacitive coupling that may appear during customer applications, atmel recommends always connecting the wp pins to a known state. when using a pull-up resistor, atmel recommends using 10k ? or less. table 4-1. write protect v cc gnd wp scl sda a 2 a 1 a 0 en eeprom xde c d out /ack logic comp load inc y dec r/w d out d in load start stop logic serial control logic h.v. pump/timing device address comparator data word addr/counter data recovery serial mux wp pin status part of the array protected atmel at24c128c at v cc full array at gnd normal read/write operations
4 atmel at24c128c [datasheet] 8734b?seepr?9/2012 5. memory organization atmel at24c128c, 128k serial eeprom : the 128k is internally organized as 256 pages of 64-bytes each. random word addressing requires a 14-bit data word address. table 5-1. pin capacitance (1) note: 1. this parameter is characterized and is not 100% tested. table 5-2. dc characteristics note: 1. v il min and v ih max are reference only and are not tested. applicable over recommended operating range from: t a = 25c, f = 1.0mhz, v cc = 1.7v to 5.5v. symbol test condition max units conditions c i/o input/output capacitance (sda) 8 pf v i/o = 0v c in input capacitance (a 0 , a 1 , a 2 , and scl) 6 pf v in = 0v applicable over recommended operating range from: t ai = -40c to +85c, v cc = 1.7v to 5.5v (unless otherwise noted) . symbol parameter test condition min typ max units v cc1 supply voltage 1.7 5.5 v i cc1 supply current v cc = 5.0v read at 400khz 1.0 2.0 ma i cc2 supply current v cc = 5.0v write at 400khz 2.0 3.0 ma i sb1 standby current v cc = 1.7v v in = v cc or v ss 1.0 ? a v cc = 5.0v 6.0 ? a i li input leakage current v cc = 5.0v v in = v cc or v ss 0.10 3.0 ? a i lo output leakage current v cc = 5.0v v out = v cc or v ss 0.05 3.0 ? a v il input low level (1) -0.6 v cc x 0.3 v v ih input high level ( (1) v cc x 0.7 v cc + 0.5 v v ol1 output low level v cc = 1.7v i ol = 0.15ma 0.2 v v ol2 output low level v cc = 3.0v i ol = 2.1ma 0.4 v
5 atmel at24c128c [datasheet] 8734b?seepr?9/2012 table 5-3. ac characteristics (industrial temperature) notes: 1. this parameter is ensured by characterization and is not 100% tested. 2. ac measurement conditions: ? r l (connects to v cc ): 1.3k (2.5v, 5.5v), 10k (1.7v) ? input pulse voltages: 0.3v cc to 0.7v cc ? input rise and fall times: 50ns ? input and output timing reference voltages: 0.5 x v cc applicable over recommended operating range from: t ai = ? 40c to +85c, v cc = 1.7v to 5.5v, cl = 100pf (unless otherwise noted). test conditions are listed in note 2 . symbol parameter 1.7v 2.5v, 5.0v units min max min max f scl clock frequency, scl 400 1000 khz t low clock pulse width low 1300 400 ns t high clock pulse width high 600 400 ns t i noise suppression time (1) 100 50 ns t aa clock low to data out valid 50 900 50 550 ns t buf time the bus must be free before a new transmission can start (1) 1300 500 ns t hd.sta start hold time 600 250 ns t su.sta start set-up time 600 250 ns t hd.dat data in hold time 0 0 ns t su.dat data in set-up time 100 100 ns t r inputs rise time (1) 300 300 ns t f inputs fall time (1) 300 100 ns t su.sto stop set-up time 600 250 ns t dh data out hold time 50 50 ns t wr write cycle time 5 5 ms endurance (1) 25c, page mode, 3.3v 1,000,000 write cycles
6 atmel at24c128c [datasheet] 8734b?seepr?9/2012 6. device operation clock and data transitions: the sda pin is normally pulled high with an external device. data on the sda pin may change only during scl low time periods (see figure 6-1 ). data changes during scl high periods will indicate a start or stop condition as defined below. figure 6-1. data validity start condition : a high-to-low transition of sda with scl high is a start condition that must precede any other command (see figure 6-2 ). figure 6-2. start and stop definition stop condition: a low-to-high transition of sda with scl high is a stop condition. after a read sequence, the stop command will place the eeprom in a standby power mode (see figure 6-2 ). acknowledge: all addresses and data words are serially transmitted to and from the eeprom in 8-bit words. the eeprom sends a zero during the ninth clock cycle to acknowledge that it has received each word. standby mode: at24c128c features a low-power standby mode that is enabled upon power-up and after the receipt of the stop bit and the completion of any internal operations. sda scl data change data stable data stable sda scl start stop
7 atmel at24c128c [datasheet] 8734b?seepr?9/2012 software reset : after an interruption in protocol, power loss or system reset, any 2-wire part can be protocol reset by following these steps: 1. create a start bit condition 2. clock nine cycles 3. create another start bit followed by stop bit condition as shown below. the device is ready for next communication after above steps has been completed. figure 6-3. software reset figure 6-4. bus timing scl sda 9 8 3 2 1 start bit start bit stop bit dummy clock cycles scl sda in sda out t f t high t low t low t r t aa t dh t buf t su.sto t su.dat t hd.dat t hd.sta t su.sta
8 atmel at24c128c [datasheet] 8734b?seepr?9/2012 figure 6-5. write cycle timing note: 1. the write cycle time t wr is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle. figure 6-6. output acknowledge scl sda t wr (1) stop condition start condition word n ack 8 th bit scl data in data out start acknowledge 9 8 1
9 atmel at24c128c [datasheet] 8734b?seepr?9/2012 7. device addressing the 128k eeprom requires an 8-bit device address word following a start condition to enable the chip for a read or write operation ( figure 7-1 ). the device address word consists of a mandatory one, zero sequence for the first four most significant bits as shown. this is common to all 2-wire eeprom devices. figure 7-1. device addressing the next three bits are the a2, a1, and a0 device address bits to allow as many as eight devices on the same bus. these bits must compare to their corresponding hard wired input pins. the a 2 , a 1 , and a 0 pins use an internal proprietary circuit that biases them to a logic low condition if the pins are allowed to float. the eighth bit of the device address is the read/write operation select bit. a read operation is initiated if this bit is high, and a write operation is initiated if this bit is low. upon a compare of the device address, the eeprom will output a zero. if a compare is not made, the device will return to a standby state. data security: at24c128c has a hardware data protection scheme that allows the user to write protect the whole memory when the wp pin is at v cc . 1 0 1 0 a2a1a0r/ w msb lsb
10 atmel at24c128c [datasheet] 8734b?seepr?9/2012 8. write operations byte write : a write operation requires two 8-bit data word addresses following the device address word and acknowledgment. upon receipt of this address, the eeprom will again respond with a zero, and then clock in the first 8-bit data word. following receipt of the 8-bit data word, the eeprom will output a zero. the addressing device, such as a microcontroller, must then terminate the write sequence with a stop condition. at this time, the eeprom enters an internally-timed write cycle, t wr , to the nonvolatile memory. all inputs are disabled during this write cycle and the eeprom will not respond until the write is complete (see figure 7-1 ). figure 8-1. byte write note: * = don?t care bit page write: the 128k eeprom is capable of 64-byte page writes. a page write is initiated the same way as a byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. instead, after the eeprom acknowledges receipt of the first data word, the microcontroller can transmit up to 63 more data words. the eeprom will respond with a zero after each data word received. the microcontroller must terminate the page write sequence with a stop condition (see figure 8-2 ). figure 8-2. page write note: * = don?t care bit the data word address lower six bits are internally incremented following the receipt of each data word. the higher data word address bits are not incremented, retaining the memory page row location. when the word address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. if more than 64 data words are transmitted to the eeprom, the data word address will roll-over and the previous data will be overwritten. the address roll-over during write is from the last byte of the current page to the first byte of the same page. acknowledge polling : once the internally-timed write cycle has started and the eeprom inputs are disabled, acknowledge polling can be initiated. this involves sending a start condition followed by the device address word. the read/write bit is representative of the operation desired. only if the internal write cycle has completed will the eeprom respond with a zero, allowing the read or write sequence to continue. s t a r t w r i t e s t o p device address first word address second word address data sda line m s b a c k r / w a c k a c k a c k sda line s t a r t w r i t e device address first word address second word address data (n) data (n + x) m s b a c k r / w a c k a c k a c k a c k s t o p
11 atmel at24c128c [datasheet] 8734b?seepr?9/2012 9. read operations read operations are initiated the same way as write operations with the exception that the read/write select bit in the device address word is set to one. there are three read operations: ? current address read ? random address read ? sequential read current address read : the internal data word address counter maintains the last address accessed during the last read or write operation, incremented by one. this address stays valid between operations as long as the chip power is maintained. the address roll-over during read is from the last byte of the last memory page, to the first byte of the first page. once the device address with the read/write select bit set to one is clocked in and acknowledged by the eeprom, the current address data word is serially clocked out. the microcontroller does not respond with an input zero but does generate a following stop condition (see figure 9-1 ). figure 9-1. current address read random read: a random read requires a dummy byte write sequence to load in the data word address. once the device address word and data word address are clocked in and acknowledged by the eeprom, the microcontroller must generate another start condition. the microcontroller now initiates a current address read by sending a device address with the read/write select bit high. the eeprom acknowledges the device address and serially clocks out the data word. the microcontroller does not respond with a zero but does generate a following stop condition. (see figure 9-2 ) figure 9-2. random read note: * = don?t care bit sda line s t a r t device address r e a d s t o p m s b a c k r / w n o a c k data sda line s t a r t s t a r t r e a d w r i t e s t o p device address second word address device address first word address data (n) m s b a c k a c k a c k l s b a c k n o a c k r / w dummy write r / w
12 atmel at24c128c [datasheet] 8734b?seepr?9/2012 sequential read: sequential reads are initiated by either a current address read or a random address read. after the microcontroller receives a data word, it responds with an acknowledge. as long as the eeprom receives an acknowledge, it will continue to increment the data word address and serially clock out sequential data words. when the memory address maximum address is reached, the data word address will roll-over and the sequential read will continue from the beginning of the array. the sequential read operation is terminated when the microcontroller does not respond with a zero but does generate a following stop condition (see figure 9-3 ). figure 9-3. sequential read note: * = don?t care bit sda line s t a r t s t a r t r e a d w r i t e s t o p device address second word address device address first word address data (n + 1) data (n + 2) data (n + x) data (n) m s b a c k a c k a c k l s b a c k a c k a c k a c k n o a c k r / w dummy write . . . . . . r / w
13 atmel at24c128c [datasheet] 8734b?seepr?9/2012 10. ordering code detail atmel designator product family device density device revision shipping carrier option operating voltage package option 128 = 128k 24c = standard i 2 c serial eeprom b = bulk (tubes) t = tape and reel m = 1.7v to 5.5v ss = jedec soic x = tssop ma = udfn me = xdfn c = vfbga wwu = wafer unsawn wdt = die in tape and reel package device grade or wafer/die thickness h = green, nipdau lead finish, industrial temperature range (-40c to +85c) u = green, matte sn lead finish, industrial temperature range (-40c to +85c) 11 = 11mil wafer thickness at24c128c-sshm-b
14 atmel at24c128c [datasheet] 8734b?seepr?9/2012 11. part markings drawing no. rev. title 24c128csm d 9/19/12 24c128csm , at24c128c standard package marking information package mark contact: dl-cso-assy_eng@atmel.com aaaaaaaa 2dc% @ atmlhyww 8-lead soic 8-lead tssop aaaaaaa 2dc% @ athyww 2dc yxx 8-lead xdfn 8-lead udfn ### hm@ yxx 2.0 x 3.0 mm body 1.8 x 2.2 mm body note 2: package drawings are not to scale note 1: designates pin 1 at24c128c: package marking information 2dcu @ymxx 2.35 x 3.73 mm body 8-ball vfbga catalog number truncation at24c128c truncation code ###: 2dc date codes voltages y = year m = month ww = work week of assembly % = minimum voltage 2: 2012 6: 2016 a: january 02: week 2 m: 1.7v min 3: 2013 7: 2017 b: february 04: week 4 4: 2014 8: 2018 ... ... 5: 2015 9: 2019 l: december 52: week 52 country of assembly lot number grade/lead finish material @ = country of assembly aaa...a = atmel wafer lot number u: industrial/matte tin h: industrial/nipdau trace code atmel truncation xx = trace code (atmel lot numbers correspond to code) at: atmel example: aa, ab.... yz, zz atm: atmel atml: atmel
15 atmel at24c128c [datasheet] 8734b?seepr?9/2012 12. ordering codes 12.1 atmel at24c128c ordering information notes: 1. bulk delivery in tubes: ? soic and tssop = 100 per tube 2. tape and reel delivery: ? soic = 4k per reel ? tssop, udfn, xdfn, and vfbga = 5k per reel 3. contact atmel sales for wafer sales. ordering code package voltage operating range at24c128c-sshm-b (1) 8s1 1.7v to 5.5v lead-free/halogen-free industrial temperature ( ? 40c to 85c) AT24C128C-SSHM-T (2) at24c128c-xhm-b (1) 8x at24c128c-xhm-t (2) at24c128c-mahm-t (2) 8ma2 at24c128c-mehm-t (2) 8me1 at24c128c-cum-t (2) 8u2-1 at24c128c-wwu11m (3) wafer sale 1.7v to 5.5v industrial temperature ( ? 40c to 85c) package type 8s1 8-lead, 0.150? wide, plastic gull wing small outline package (jedec soic) 8x 8-lead, 4.40mm body, plastic thin shrink small outline package (tssop) 8ma2 8-pad, 2.00mm x 3.00mm body, 0.50mm pitch, dual no lead package (udfn) 8me1 8-pad, 1.80mm x 2.20mm body, extra thin dfn package (xdfn) 8u2-1 8-ball, die ball grid array package (vfbga)
16 atmel at24c128c [datasheet] 8734b?seepr?9/2012 13. packaging information 13.1 8s1 ? 8-lead jedec soic drawing no. rev. title gpc common dimensions (unit of measure = mm) symbol min nom max note a1 0.10 ? 0.25 a 1.35 ? 1.75 b 0.31 ? 0.51 c 0.17 ? 0.25 d 4.80 ? 5.05 e1 3.81 ? 3.99 e 5.79 ? 6.20 e 1.27 bsc l 0.40 ? 1.27 ? ? 0 ? 8 ? e 1 n top view c e1 end view a b l a1 e d side view package drawing contact: packagedrawings@atmel.com 8s1 g 6/22/11 notes: this drawing is for general information only. refer to jedec drawing ms-012, variation aa for proper dimensions, tolerances, datums, etc. 8s1, 8-lead (0.150? wide body), plastic gull wing small outline (jedec soic) swb
17 atmel at24c128c [datasheet] 8734b?seepr?9/2012 13.2 8x ? 8-lead tssop drawing no. rev. title gpc common dimensions (unit of measure = mm) symbol min nom max note a - - 1.20 a1 0.05 - 0.15 a2 0.80 1.00 1.05 d 2.90 3.00 3.10 2, 5 e 6.40 bsc e1 4.30 4.40 4.50 3, 5 b 0.19 ? 0.30 4 e 0.65 bsc l 0.45 0.60 0.75 l1 1.00 ref c 0.09 - 0.20 side view end view top view a2 a l l1 d 1 e1 n b pin 1 indicator this corner e e notes: 1. this drawing is for general information only. refer to jedec drawing mo-153, variation aa, for proper dimensions, tolerances, datums, etc. 2. dimension d does not include mold flash, protrusions or gate burrs. mold flash, protrusions and gate burrs shall not exceed 0.15mm (0.006in) per side. 3. dimension e1 does not include inter-lead flash or protrusions. inter-lead flash and protrusions shall not exceed 0.25mm (0.010in) per side. 4. dimension b does not include dambar protrusion. allowable dambar protrusion shall be 0.08mm total in excess of the b dimension at maximum material condition. dambar cannot be located on the lower radius of the foot. minimum space between protrusion and adjacent lead is 0.07mm. 5. dimension d and e1 to be determined at datum plane h. package drawing contact: packagedrawings@atmel.com 8x d 6/22/11 8x, 8-lead 4.4mm body, plastic thin shrink small outline package (tssop) tnr c a1
18 atmel at24c128c [datasheet] 8734b?seepr?9/2012 13.3 8ma2 ? 8-pad udfn title drawing no. gpc rev. package drawing contact: packagedrawings@atmel.com 8ma2 ynz c 8ma2, 8-pad, 2 x 3 x 0.6 mm body, thermally enhanced plastic ultra thin dual flat no lead package (udfn) common dimensions (unit of measure = mm) symbol min nom max note d 1.90 2.00 2.10 e 2.90 3.00 3.10 d2 1.40 1.50 1.60 e2 1.20 1.30 1.40 a 0.50 0.55 0.60 a1 0.0 0.02 0.05 a2 ? ? 0.55 c 0.152 ref l 0.30 0.35 0.40 e 0.50 bsc b 0.18 0.25 0.30 3 k 0.20 ? ? 9/6/12 d2 e2 e e (6x) l (8x) b (8x) pin#1 id a a1 a2 pin 1 id d c k 8 7 6 5 1 2 3 4 1 2 3 4 8 7 6 5
19 atmel at24c128c [datasheet] 8734b?seepr?9/2012 13.4 8me1 ? 8-pad xdfn package drawing contact: packagedrawings@atmel.com gpc drawing no. rev. title common dimensions (unit of measure = mm) dtp symbol min nom max note ? 0.00 1.70 2.10 0.15 0.26 a a1 d e b e e1 l ? ? 1.80 2.20 0.20 0.40 typ 1.20 ref 0.30 0.40 0.05 1.90 2.30 0.25 0.35 end view 8me1 b 9/10/2012 8me1 , 8-pad (1.80mm x 2.20mm body) extra thin dfn (xdfn) top view 6 5 7 4 3 e d 8 1 2 pin #1 id 0.10 0.15 b l b e pin #1 id e1 a1 a side view
20 atmel at24c128c [datasheet] 8734b?seepr?9/2012 13.5 8u2-1 ? 8-ball vfbga drawing no. rev. title gpc package drawing contact: packagedrawings@atmel.com 8u2-1 f 3/20/12 8u2-1, 8-ball, 2.35 x 3.73 mm body, 0.75 mm pitch, vfbga package gww common dimensions (unit of measure = mm) symbol min nom max note a 0.81 0.91 1.00 a1 0.15 0.20 0.25 a2 0.40 0.45 0.50 b 0.25 0.30 0.35 d 2.35 bsc e 3.73 bsc e 0.75 bsc e1 0.74 ref d 0.75 bsc d1 0.80 ref 2. dimension 'b' is measured at the maximum solder ball diameter. 1. this drawing is for general information. 3. solder ball composition shall be 95.5sn-4.0ag-.5cu. notes: a d 0.08 c c f 0.10 c a1 a2 ?b j n 0.15 m cab j n 0.08 m c a (4x) d 0.10 b a1 ball pad corner d e side view top view e (e1) d 21 d c b a a1 ball pad corner (d1) 8 solder balls bottom view
21 atmel at24c128c [datasheet] 8734b?seepr?9/2012 14. revision history doc. rev. date comments 8734b 09/2012 update udfn package drawing. update template and atmel logo. 8734a 04/2011 inital document release.
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